Feflow error help!!

When I run Feflow and open the DAC file, an error message occurs.
Array length mismatch (# of diagram timesteps)!
Should I re-simulate it? Please tell me how to fix it.

General results should be fine, just the content of the diagrams may be corrupt. Possible reasons from my experience: Saving interrupted (due to full disk, etc.), version differences between writing (simulation) and reading DAC.

I checked your answer, but it doesn't. DAC file cannot be loaded. There is no further progress in the message in the attached picture. Is there any other workaround? Please help.

In case that there are many time steps in the dac file, loading can take long (possibly hours for very large files). The reason for this is that FEFLOW will reconstruct the damaged diagram data from the results of all the time steps as far as possible. Thus each time step has to be loaded (one after another) in order to extract the corresponding data.